1. Field of the Invention
The present invention relates to a memory control circuit in a memory card for driving and controlling memory chips incorporated therein.
2. Detailed Description of the Related Art
FIGS. 8 and 9 of the accompanying drawings are block diagrams schematically showing a relationship between a memory control circuit and memory chips incorporated in a conventional memory card, wherein FIG. 8 relates to an SRAM (Static Random Access Memory) card (volatile memory card) incorporating SRAM, while FIG. 9 relates to a MIX card (hybrid memory card) incorporating SRAM and non-volatile ROM (Read Only Memory) in a mixed state. In both FIGS., the numerals designate respectively: 1, a memory control circuit; 2, an SRAM chip; 3, a ROM chip; 4, a data backup built-in battery; 5, a power source without backup indicated by a circle (hereinafter referred to as A power source); 6, a power source with backup indicated by a square (hereinafter referred to as B power source); 7, a power source control IC having a one mega ohm resistor 200 connected between Vcc and ground; 8, a memory chip enable signal bus which is composed of a plurality of memory chip enable signal output lines; 9a, a backup signal line; 9b, an address bus; and 9c, a chip enable signal line.
The A power source 5 receives power outside of the card e.g. from a terminal machine (not shown) when the card is connected thereto. The B power source 6, meanwhile, has a backup for receiving power supply from the built-in-battery 4 for maintaining data in the volatile memory even when the card is not in use. The memory control circuit (hereinafter referred to as memory control IC) 1 and the SRAM chips 2 are connected to the B power source 6, and the ROM chips not needing any backup shown in FIG. 9 are connected to the A power source 5. The power source control circuit 7 (hereinafter referred to as power source control IC) switches between both power sources 5 and 6, and generates a backup signal (BUP) indicating the backup state when there is no power supply outside of the card.
The memory control IC 1 receives an address signal (AD) and a chip enable signal (CE) from e.g. the terminal machine, and a backup signal (BUP) from the power source control IC 7, and selectively outputs memory chip enable signals to the SRAM chips 2 and the ROM chips 3 in accordance with these input signals. The SRAM chips 2 and the ROM chips 3 have memory chip enable signal input terminals (MCE1, MCE2, . . . ) to which the memory chip enable signals are input. The chips 2 and 3 are set to the states of being capable of reading or of reading/writing when the memory chip enable signal is in "L" level condition. Several other kinds of control signals such as write enable signal etc. are also input to the memory control IC 1, but are omitted to be described and illustrated here for simplification, thereby showing only the signals essentially relating to the present invention.
FIG. 10 schematically shows a composition of the memory chip enable signal generating section in the memory control IC 1. In FIG. 10, a decoder 10 becomes an enable state when its chip enable terminal (CE) is in "L" level condition to selectively supply memory chip enable signals of "L" level (MCE1, MCE2, . . . ) in accordance with the address signals (AD) . Also, the decoder 10 becomes a disable state when the chip enable terminal (CE) is in an "H" level condition to set all the memory chip enable signals (MCE1, MCE2, . . . ) to an "H" level. The backup signal (BUP) from the power source control IC 7 is in an "L" level condition during the backup state and inverted in an inverter 11 to be then supplied to an input terminal of an OR gate 12 so as to become a gate signal for a chip enable signal (CE) input to the other Input terminal of the OR gate. An output terminal of the OR gate 12 is connected to a chip enable terminal (CE) of the decoder 10.
Therefore, in both cases of FIGS. 8 and 9, the decoder 10 is disabled during the backup state, such that the "H" level memory chip enable signals (MCE) are supplied to all the SRAM chips 2 and the ROM chips 3. As a result, the chips 2 and 3 are disabled, and the SRAM chips 2 coupled to the B power source 6 are in the backup state-to maintain the stored data.
As mentioned above, in the conventional memory control circuit for the memory card, the memory chip enable signals of "H" level have been supplied to all the coupled memory chips for disabling them in the backup state. Therefore, in the case of the hybrid memory card, the "H" level memory chip enable signals were supplied even to those ROM chips not requiring any backup. This means that unnecessarily excessive currents flow through the ROM chips to cause unnecessary power consumption.